bwin必赢官网PSRAM/ONFI/SDIO/EMMC/RPC IP可提供支持JEDEC标准、兼容PSRAM器件的一站式交钥匙解决方案，低功耗、高速率、小尺寸、时序优化。支持市场上所有的 APmemory UHS PSRAM组件。PHY组件包含PSRAM专用功能和实用 IO设备、关键时序同步模块(TSM)、低抖动PLL、PSRAM接口的TX和RX逻辑控制。且PHY都预先组装了.lib、LEF和GDS，DQ总线带宽可支持8位以匹配PSRAM DQ接口，易于集成，缩短客户设计周期。该方案包括Controller和PHY，可配置时序、驱动强度参数和各种PSRAM接口，灵活高效。
The INNOSILICON DDR IPTM Mixed-Signal PSRAM PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports APmemory UHS PSRAM components in the market. The PHY components contain PSRAM specialized functional and utility IO devices, critical timing synchronization module (TSM), the low-jitter PLL, the TX and RX logic control for the PSRAM interface.
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. The DQ bus width can support 8 bit to match the PSRAM DQ interfaces. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.
The Innosilicon's PSRAM PHY solution includes PSRAM controller and PHY. With configurable timing and driving strength parameters to interface to the wide variety of PSRAMs, the PHY is very flexible with advanced command capability to increase PSRAM operation efficiency.
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